Area-efficient correlated double sampling scheme with single sampling capacitor for CMOS image sensors

Abstract

An area-efficient correlated double sampling (CDS) circuit is proposed. In conventional designs, most of the area of CDS circuits is occupied by two large on-chip sampling capacitors. A new CDS scheme is devised using only one sampling capacitor. The proposed CDS circuit has been successfully realised in a small two column pitch of 7.2 mu m in a test chip fabricated using 0.18 mu m CMOS process and has demonstrated fixed pattern noise less than 0.46%.