Development of a dual burn-in policy for semiconductor products based on the number of defective neighborhood chips

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dc.contributor.authorTong S.H.ko
dc.contributor.authorYum, Bong-Jinko
dc.date.accessioned2009-02-02T07:46:44Z-
dc.date.available2009-02-02T07:46:44Z-
dc.date.created2012-02-06-
dc.date.created2012-02-06-
dc.date.issued2006-12-
dc.identifier.citationINTERNATIONAL JOURNAL OF RELIABILITY, QUALITY AND SAFETY ENGINEERING, v.13, no.6, pp.501 - 525-
dc.identifier.issn0218-5393-
dc.identifier.urihttp://hdl.handle.net/10203/8383-
dc.description.abstractMost of the previous studies on developing an optimal burn-in policy for semiconductor products only deal with the burn-in process itself and little is concerned with utilizing the information on the quality levels of chips before being subjected to burn-in. Developed in this paper is a dual burn-in policy in which the number of chips (d) which do not pass the wafer probe (WP) test and lie in the neighborhood of a reference chip is utilized as an indicator on the quality level of that reference chip. The dual burn-in policy first classifies the chips which pass the WP test into two groups using a boundary value of d, and then each group is subject to burn-in for its own duration. For a certain type of 256M DRAM product, the performance of the proposed dual burn-in policy is compared to that of the single burn-in policy in which all chips are subjected to the burn-in of the same duration without considering d. The analysis results show that, for the cases considered, the proposed dual burn-in policy is more cost-effective than the single burn-in policy, implying that the additional information from the WP test is beneficial to establishing an efficient burn-in policy in semiconductor manufacturing. ? World Scientific Publishing Company.-
dc.languageEnglish-
dc.language.isoen_USen
dc.publisherWorld Scientific Publishing Co-
dc.titleDevelopment of a dual burn-in policy for semiconductor products based on the number of defective neighborhood chips-
dc.typeArticle-
dc.identifier.scopusid2-s2.0-33846514691-
dc.type.rimsART-
dc.citation.volume13-
dc.citation.issue6-
dc.citation.beginningpage501-
dc.citation.endingpage525-
dc.citation.publicationnameINTERNATIONAL JOURNAL OF RELIABILITY, QUALITY AND SAFETY ENGINEERING-
dc.embargo.liftdate9999-12-31-
dc.embargo.terms9999-12-31-
dc.contributor.localauthorYum, Bong-Jin-
dc.contributor.nonIdAuthorTong S.H.-
dc.subject.keywordAuthorBeta-binomial distribution-
dc.subject.keywordAuthorBurn-in-
dc.subject.keywordAuthorNeighborhood chip-
dc.subject.keywordAuthorProportional hazard model-
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