DC Field | Value | Language |
---|---|---|
dc.contributor.author | Tong S.H. | ko |
dc.contributor.author | Yum, Bong-Jin | ko |
dc.date.accessioned | 2009-02-02T07:46:44Z | - |
dc.date.available | 2009-02-02T07:46:44Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 2006-12 | - |
dc.identifier.citation | INTERNATIONAL JOURNAL OF RELIABILITY, QUALITY AND SAFETY ENGINEERING, v.13, no.6, pp.501 - 525 | - |
dc.identifier.issn | 0218-5393 | - |
dc.identifier.uri | http://hdl.handle.net/10203/8383 | - |
dc.description.abstract | Most of the previous studies on developing an optimal burn-in policy for semiconductor products only deal with the burn-in process itself and little is concerned with utilizing the information on the quality levels of chips before being subjected to burn-in. Developed in this paper is a dual burn-in policy in which the number of chips (d) which do not pass the wafer probe (WP) test and lie in the neighborhood of a reference chip is utilized as an indicator on the quality level of that reference chip. The dual burn-in policy first classifies the chips which pass the WP test into two groups using a boundary value of d, and then each group is subject to burn-in for its own duration. For a certain type of 256M DRAM product, the performance of the proposed dual burn-in policy is compared to that of the single burn-in policy in which all chips are subjected to the burn-in of the same duration without considering d. The analysis results show that, for the cases considered, the proposed dual burn-in policy is more cost-effective than the single burn-in policy, implying that the additional information from the WP test is beneficial to establishing an efficient burn-in policy in semiconductor manufacturing. ? World Scientific Publishing Company. | - |
dc.language | English | - |
dc.language.iso | en_US | en |
dc.publisher | World Scientific Publishing Co | - |
dc.title | Development of a dual burn-in policy for semiconductor products based on the number of defective neighborhood chips | - |
dc.type | Article | - |
dc.identifier.scopusid | 2-s2.0-33846514691 | - |
dc.type.rims | ART | - |
dc.citation.volume | 13 | - |
dc.citation.issue | 6 | - |
dc.citation.beginningpage | 501 | - |
dc.citation.endingpage | 525 | - |
dc.citation.publicationname | INTERNATIONAL JOURNAL OF RELIABILITY, QUALITY AND SAFETY ENGINEERING | - |
dc.embargo.liftdate | 9999-12-31 | - |
dc.embargo.terms | 9999-12-31 | - |
dc.contributor.localauthor | Yum, Bong-Jin | - |
dc.contributor.nonIdAuthor | Tong S.H. | - |
dc.subject.keywordAuthor | Beta-binomial distribution | - |
dc.subject.keywordAuthor | Burn-in | - |
dc.subject.keywordAuthor | Neighborhood chip | - |
dc.subject.keywordAuthor | Proportional hazard model | - |
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