A low-jitter delay-locked loop with harmonic-lock prevention

Abstract

A multiphase low-jitter delay-locked loop (DLL) with harmonic-lock prevention, targeted at a gigabit parallel link interface, is delineated. A three-input four-state dynamic phase detector (PD) is proposed to obviate harmonic locking. Employing a low-jitter delay element and a new type of PD, the DLL is compact and feasible in its nature. The DLL is designed using a 0.35 mum 2P4M CMOS process with 3.3 V supply. Experimental results show that the circuit avoids false locking.