DC Field | Value | Language |
---|---|---|
dc.contributor.author | Park, Sin Chong | ko |
dc.contributor.author | Yoo, C | ko |
dc.contributor.author | Park, SC | ko |
dc.date.accessioned | 2013-03-04T09:41:08Z | - |
dc.date.available | 2013-03-04T09:41:08Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 2002-02 | - |
dc.identifier.citation | IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, v.E85A, no.2, pp.505 - 507 | - |
dc.identifier.issn | 0916-8508 | - |
dc.identifier.uri | http://hdl.handle.net/10203/82329 | - |
dc.description.abstract | A multiphase low-jitter delay-locked loop (DLL) with harmonic-lock prevention, targeted at a gigabit parallel link interface, is delineated. A three-input four-state dynamic phase detector (PD) is proposed to obviate harmonic locking. Employing a low-jitter delay element and a new type of PD, the DLL is compact and feasible in its nature. The DLL is designed using a 0.35 mum 2P4M CMOS process with 3.3 V supply. Experimental results show that the circuit avoids false locking. | - |
dc.language | English | - |
dc.publisher | IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG | - |
dc.title | A low-jitter delay-locked loop with harmonic-lock prevention | - |
dc.type | Article | - |
dc.identifier.wosid | 000173951000032 | - |
dc.type.rims | ART | - |
dc.citation.volume | E85A | - |
dc.citation.issue | 2 | - |
dc.citation.beginningpage | 505 | - |
dc.citation.endingpage | 507 | - |
dc.citation.publicationname | IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES | - |
dc.contributor.localauthor | Park, Sin Chong | - |
dc.contributor.nonIdAuthor | Yoo, C | - |
dc.contributor.nonIdAuthor | Park, SC | - |
dc.type.journalArticle | Letter | - |
dc.subject.keywordAuthor | four-state dynamic phase detector | - |
dc.subject.keywordAuthor | harmonic locking | - |
dc.subject.keywordAuthor | DLL | - |
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