Browse "School of Computing(전산학부)" by Author 1554
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| On Load Latency in Low-Power Caches Kim, Soontae; Vijaykrishnan, N.; Irwin, M.J.; John, L.K., Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. (ISLPED '03) , pp.258 - 261, 2003-08-01 |
| Performance modeling using hardware performance counters Kim, Soontae, Triangle Symposium on Advanced ICT, 2010-01-25 |
| Power-aware Partitioned Cache Architectures Kim, Soontae; Kandemir, M.; Sivasubramaniam, A.; Irwin, M.J.; Geethanjali, E., ACM/IEEE International Symposium on Low Power Electronics and Design, pp.64 - 67, 2001-08 |
| Predictive Precharging for Bitline Leakage Energy Reduction Kim, Soontae; Vijaykrishnan, N.; Kandemir, M.; Irwin, M.J., 15th Annual IEEE International ASIC/SOC Conference, 2002. , pp.36 - 40, 2002-09 |
| Reducing ALU and Register File Energy by Dynamic Zero Detection Kim, Soontae, International Performance Computing and Communication Conference, pp.365 - 371, IEEE Internationa Performance, Computing, and Communications Conference, 2007. (IPCCC 2007), 2007-04 |
| Resuscitating Privacy-Preserving Mobile Payment with Customer in Complete Control Konidala, Divyan M.; Dwijaksara, Made H; Kim, Kwangjo; Lee, Dongman; Lee, Byoungcheon; Kim, Daeyoung; Kim, Soontae, International Workshop on Smartphone Applications and Services, 2010-12-09 |
| Scheduling Reusable Instructions for Power Reduction Hu, J.S.; Vijaykrishnan, N.; Kim, Soontae; Kandemir, M.; Irwin, M.J., Proceedings Design, Automation and Test in Europe Conference and Exhibition, 2004. , v.1, pp.148 - 153, 2004-02 |
| SimTag: Exploiting tag bits similarity to improve the reliability of the data caches Kim, Jesung; Kim, Soontae; Lee, Yebin, Design, Automation and Test in Europe Conference and Exhibition, DATE 2010, pp.941 - 944, 2010-03-08 |
| TEPS: Transient error protection utilizing sub-word parallelism Hong, Seokin; Kim, Soontae, 2009 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2009, pp.286 - 291, 2009-05-14 |
| Use of local memory for efficient Java execution Tomar, S.; Kim, Soontae; Vijaykrishnan, N.; Kandemir, M.; Irwin, M.J., IEEE International Conference on Computer Design, pp.468 - 473, 2001-09 |
| Write buffer-oriented energy reduction in the L1 data cache of two-level caches for the embedded system Kim, Soontae; Lee, Jongmin, 20th Great Lakes Symposium on VLSI, GLSVLSI 2010, pp.257 - 262, 2010-05-16 |
| 내장형 시스템을 위한 저전력 2-레벨 캐쉬 메모리의 설계 김용호; 박수호; 김경아; 김순태; 이종민, 제30회 한국정보처리학회 추계학술발표대회 , pp.0 - 0, 2008-11-15 |
| 셀특성화 테이블 생성시 타이밍 에러를 최소화하기 김순태, 정보과학회 학술대회 발표논문집, pp.0 - 0, 1997-04-01 |
| 최적 특성화 테이블 생성 시스템 김순태, 한국정보과학회 학술대회, pp.0 - 0, 1997-10-01 |
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