Dual-Loop Digital PLL for Adaptive Clock Recovery

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Publisher
대한전자공학회
Issue Date
1997-12
Language
English
Citation

CAD 및 VLSI 설계연구회지, v.6, no.1, pp.131 - 143

URI
http://hdl.handle.net/10203/73192
Appears in Collection
RIMS Journal Papers
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