Dual-Loop Digital PLL for Adaptive Clock Recovery
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | 김태훈 | ko |
| dc.contributor.author | 김범섭 | ko |
| dc.date.accessioned | 2013-02-28T06:16:29Z | - |
| dc.date.available | 2013-02-28T06:16:29Z | - |
| dc.date.created | 2012-02-06 | - |
| dc.date.created | 2012-02-06 | - |
| dc.date.issued | 1997-12 | - |
| dc.identifier.citation | CAD 및 VLSI 설계연구회지, v.6, no.1, pp.131 - 143 | - |
| dc.identifier.uri | http://hdl.handle.net/10203/73192 | - |
| dc.language | English | - |
| dc.publisher | 대한전자공학회 | - |
| dc.title | Dual-Loop Digital PLL for Adaptive Clock Recovery | - |
| dc.type | Article | - |
| dc.type.rims | ART | - |
| dc.citation.volume | 6 | - |
| dc.citation.issue | 1 | - |
| dc.citation.beginningpage | 131 | - |
| dc.citation.endingpage | 143 | - |
| dc.citation.publicationname | CAD 및 VLSI 설계연구회지 | - |
| dc.contributor.localauthor | 김범섭 | - |
| dc.contributor.nonIdAuthor | 김태훈 | - |
- Appears in Collection
- RIMS Journal Papers
- Files in This Item
- There are no files associated with this item.
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.