| 1 | 1.2-mW Online Learning Mixed-Mode Intelligent Inference Engine for Low-Power Real-Time Object Recognition Processor Oh, Jin-Wook; Lee, Seung-Jin; Yoo, Hoi-Jun, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.21, no.5, pp.921 - 933, 2013-05 |
| 2 | 2차원 DWT의 준-순환적 구조 = Semi-recursive VLSI architecture of 2-D discrete wavelet transformlink 전현규; Jeon, Hyun-Kyu; et al, 한국과학기술원, 1997 |
| 3 | 81.6 GOPS Object Recognition Processor Based on a Memory-Centric NoC Kim, Dong-Hyun; Kim, Kwan-Ho; Kim, Joo-Young; Lee, Seung-Jin; Lee, Se-Joong; Yoo, Hoi-Jun, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.17, no.3, pp.370 - 383, 2009-03 |
| 4 | A 2.74-pJ/bit, 17.7-Gb/s Iterative Concatenated-BCH Decoder in 65-nm CMOS for NAND Flash Memory Lee, Youngjoo; Yoo, Hoyoung; Jung, Jaehwan; Jo, Jihyuck; Park, In-Cheol, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.48, no.10, pp.2531 - 2540, 2013-10 |
| 5 | A dual burn-in policy for defect-tolerant memory products using the number of repairs as a quality indicator Tong, SH; Yum, Bong-Jin, MICROELECTRONICS RELIABILITY, v.48, pp.471 - 480, 2008-03 |
| 6 | A hierarchical circuit clustering algorithm with stable performance Kyoung, SJ; Seong, KS; Park, In-Cheol; Kyung, Chong-Min, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, v.E82A, no.9, pp.1987 - 1993, 1999-09 |
| 7 | A programmable 3.2-GOPS merged DRAM logic for video signal processing Chang, SH; Kim, BS; Kim, Lee-Sup, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY, v.10, no.6, pp.967 - 973, 2000-09 |
| 8 | (A) fast programmable high precision nonvolatile analog memory for VLSI neural network = VLSI 신경회로망을 위한 고속 정밀 비휘발성 아날로그 기억소자link Kim, Kyu-Hyoun; 김규현; et al, 한국과학기술원, 1998 |
| 9 | Analysis and architecture design of binary arithmetic coder for JPEG2000 = JPEG2000의 binary arithmetic coder에 관한 분석 및 아키텍처 구성link Rhu, Min-Soo; 유민수; et al, 한국과학기술원, 2009 |
| 10 | Bandwidth-efficient mobile geometry processor with tessellation functionality and power-saving techniques = 효율적 메모리 대역폭 사용과 전력소모 감소를 위한 테셀레이션 가능 모바일 기하 프로세서에 관한 연구link Chung, Kyu-Sik; 정규식; et al, 한국과학기술원, 2009 |
| 11 | Block-matching criterion for efficient VLSI implementation of motion estimation Baek, YJ; Oh, HS; Lee, Heung-Kyu, ELECTRONICS LETTERS, v.32, no.13, pp.1184 - 1185, 1996-06 |
| 12 | Characteristics of tunneling nitride grown by electron cyclotron resonance nitrogen-plasma nitridation and its application to low-voltage electrical erasable-programmable read-only memory Min, KS; Chung, JY; Lee, Kwyro, JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES REVIEW PAPERS, v.40, no.4B, pp.2963 - 2968, 2001-04 |
| 13 | Charge recycling differential logic for low power VLSI system = 저 전력 VLSI 시스템을 위한 전하 재활용 차동 회로의 연구link Kong, Bai-Sun; 공배선; et al, 한국과학기술원, 1996 |
| 14 | CIRCUIT PLACEMENT ON ARBITRARILY SHAPED REGIONS USING THE SELF-ORGANIZATION PRINCIPLE KIM, SS; Kyung, Chong-Min, IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.11, no.7, pp.844 - 854, 1992-07 |
| 15 | Dual-issue real-time CABAC decoder for high definition H.264/AVC bitstream = 고화질 H.264/AVC 영상용 이중 이슈 실시간 CABAC 복호기link Son, Won-Hee; 손원희; et al, 한국과학기술원, 2009 |
| 16 | Energy-Efficient Symmetric BC-BCH Decoder Architecture for Mobile Storages Hwang, Seokha; Moon, Seungsik; Jung, Jaehwan; Kim, Daesung; Park, In-Cheol; Ha, Jeongseok; Lee, Youngjoo, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-I: REGULAR PAPERS, v.66, no.11, pp.4462 - 4475, 2019-11 |
| 17 | High-Throughput and Area-Efficient MIMO Symbol Detection Based on Modified Dijkstras Search Kim, Tae-Hwan; Park, In-Cheol, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.57, no.7, pp.1756 - 1766, 2010-07 |
| 18 | High-Throughput and Low-Complexity BCH Decoding Architecture for Solid-State Drives Lee, Youngjoo; Yoo, Hoyoung; Yoo, Injae; Park, In-Cheol, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.22, no.5, pp.1183 - 1187, 2014-05 |
| 19 | High-throughput and small-area sphere decoders for MIMO communication Systems = MIMO 통신 시스템을 위한 고성능 저면적의 스피어 디코더link Kim, Tae-Hwan; 김태환; et al, 한국과학기술원, 2010 |
| 20 | Low-power and area-efficient FIR filter implementation suitable for multiple taps Kim, KS; Lee, Kwyro, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.11, pp.150 - 153, 2003-02 |
| 21 | MIMO detector based on trellis structure Lee, Jin; Park, Sin Chong, IEICE TRANSACTIONS ON COMMUNICATIONS, v.E91B, no.3, pp.951 - 954, 2008-03 |
| 22 | Power distribution-analysis of VLSI interconnects using model order reduction Shin, Youngsoo; Sakurai, T, IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.21, no.6, pp.739 - 745, 2002-06 |
| 23 | Power Gating: Circuits, Design Methodologies, and Best Practice for Standard-Cell VLSI Designs Shin, Young-Soo; Seomun, Jun; Choi, Kyu-Myung; Sakurai, Takayasu, ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, v.15, no.4, 2010-09 |
| 24 | Quasi-Primitive Block-Wise Concatenated BCH Codes With Collaborative Decoding for NAND Flash Memories Kim, Daesung; Ha, Jeongseok, IEEE TRANSACTIONS ON COMMUNICATIONS, v.63, no.10, pp.3482 - 3496, 2015-10 |
| 25 | Scalable VLSI architectures for lattice structure-based discrete wavelet transform Kim, JT; Lee, Yong-Hoon; Isshiki, T; Kunieda, H, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING, v.45, no.8, pp.1031 - 1043, 1998-08 |
| 26 | Shader-based tessellation to save memory bandwidth in a mobile multimedia processor Chung, Kyusik; Yu, Chang-Hyo; Kim, Donghyun; Kim, Lee-Sup, COMPUTERS & GRAPHICS-UK, v.33, no.5, pp.625 - 637, 2009-10 |
| 27 | Visual Image Processing RAM: Memory Architecture With 2-D Data Location Search and Data Consistency Management for a Multicore Object Recognition Processor Kim, Joo-Young; Kim, Dong-Hyun; Lee, Seung-Jin; Kim, Kwan-Ho; Yoo, Hoi-Jun, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY, v.20, no.4, pp.485 - 495, 2010-04 |
| 28 | VLSI architecture for wavelet vector quantization in wireless image communication = 무선 영상 통신을 위한 웨이블릿 벡터 양자화의 VLSI 구조 연구link Paek, Seung-Kwon; 백승권; et al, 한국과학기술원, 1999 |
| 29 | VLSI design using redundant binary number system : arithmetic components for floating-point datapath unit = 잉여 이진수 시스템을 이용한 VLSI 시스템 설계 : 부동소수점 연산기로의 적용link Han, Kyung-Nam; 한경남; et al, 한국과학기술원, 2002 |
| 30 | VLSI implementation for high-throughput turbo decoder with parallel architecture = 병렬 구조를 가지는 고속 터보 디코드의 VLSI 구현link Kwak, Jae-Young; 곽재영; et al, 한국과학기술원, 2003 |
| 31 | VLSI implementation of the real value based list sphere decoder(LSD) for the MIMO wireless communication system = 다중 입추력 무선 통신 시스템을 위한 real value 기반 list sphere decoder(LSD)의 VLSI 설계link Seo, Sang-Ho; 서상호; et al, 한국정보통신대학교, 2006 |
| 32 | 독립 성분 분석 기법과 최대치 해석에 기반한 내장형 잡음 하 음성 인식 시스템에 관한 연구 = Study on embedded noise-robust speech recognition system based on independent component analysis and peak analysislink 김창민; Kim, Chang-Min; et al, 한국과학기술원, 2004 |
| 33 | 저전력 롬 공유 DCT/IDCT processor의 설계 = Design of a low-power ROM shared DCT/IDCT processorlink 권병섭; Kwon, Byung-Sup; et al, 한국과학기술원, 1997 |
| 34 | 프랙탈 압축 영상의 복원을 위한 디코더의 VLSI 구현 = VLSI implementation of decoder for decompressing fractal-based compressed imagelink 김경훈; Kim, Kyung-Hoon; et al, 한국과학기술원, 1998 |
