This paper describes fast and accurate nonvolatile analog memories based on EEPROM for the main application as a synaptic weight storage device of VLSI neural network. Two kinds of novel programming schemes have been proposed to overcome significant problems in conventional EEPROM. Test devices for each scheme have been designed, fabricated and measured to prove outstanding performances in programming speed and accuracy.
Coupling Charge Balancing Scheme (CCBS) has been proposed to overcome capacitive coupling problem allowing us to program and read (verify) simultaneously and as a result, to program within single pulse. Basic CCBS cell with self-convergent feedback circuitry exhibits the programming speed faster than that of conventional ones by 2~3 or more orders. One variation, D-CCBS (Differential-CCBS) is also proposed to compensate for the temperature and process variations in CCBS.
Differentially Balanced Constant tunneling current Scheme (DBCS) has been proposed to overcome both capacitive coupling and self limiting problems. Constant programming rate with single program pulse has been achieved, which drastically enhances the programming speed, accuracy and device reliability. A prototype chip containing 8×128 NVAM cells (cell size of 9×13.6μ㎡) has been fabricated using 0.8㎛ CMOS. Each cell is measured to store more than 8bit (256 levels) within 360㎲ which is even comparable to that of conventional digital EEPROM. DBCS exhibits the theoretically fastest programming speed of analog memory based on EEPROM.
Hyper loop, a conditionally computing neural network has been introduced as a completely new conceptual methodology for the implementation of VLSI neural network in fully digital manner. It can substitute most of arithmetic multiplication operations in conventional directly implemented VLSI neural network for arithmetic subtraction and Boolean operations drastically reducing the total number of multipliers which has been a bottle-neck in integrating l...