Browse "College of Engineering(공과대학)" by Subject VIAS
Showing results 1 to 7 of 7
| An angular distribution function for the sputter-depositing atoms and general equations describing the initial thickness profile of a thin film deposited inside a via and trench by sputtering Kim, Chang-Gyu; Lee, Won-Jong, THIN SOLID FILMS, v.519, no.1, pp.74 - 80, 2010-10 |
| An Efficient Crosstalk-Included Eye-Diagram Estimation Method for High-Speed Interposer Channel on 2.5-D and 3-D IC Choi, Sumin; Kim, Hee-Gon; Jung, Daniel Hyunsuk; Kim, Jonghoon J.; Lim, Jaemin; Kim, Joungho, IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY, v.59, no.3, pp.927 - 939, 2017-06 |
| An Improved 100 GHz Equivalent Circuit Model of a Through Silicon Via With Substrate Current Loop Kim, Kibeom; Hwang, Karam; Ahn, Seungyoung, IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, v.26, no.6, pp.425 - 427, 2016-06 |
| Filling of very fine via holes for three-dimensional packaging by using ionized metal plasma sputtering and electroplating Cho, Byeong-Hoon; Yun, Jae-Jin; Lee, Won-Jong, JAPANESE JOURNAL OF APPLIED PHYSICS, v.46, no.45-49, pp.L1135 - L1137, 2007-12 |
| Optimization of deep reactive ion etching for microscale silicon hole arrays with high aspect ratio Kim, Taeyeong; Lee, Jungchul, MICRO AND NANO SYSTEMS LETTERS, v.10, no.1, 2022-09 |
| Rigorous mathematical model of through-silicon via capacitance Kim, Kibeom; Kim, Jedok; Kim, Hongkyun; Ahn, Seungyoung, IET CIRCUITS DEVICES & SYSTEMS, v.12, no.5, pp.589 - 593, 2018-09 |
| Through-Silicon Via Capacitance-Voltage Hysteresis Modeling for 2.5-D and 3-D IC Kim, Dong-Hyun; Kim, Youngwoo; Cho, Jong-Hyun; Bae, Bumhee; Park, Junyong; Lee, Hyunsuk; Lim, Jaemin; et al, IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, v.7, no.6, pp.925 - 935, 2017-06 |
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