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Showing results 4 to 11 of 11

4
Memory device supporting rank-level parallelism and memory system including the same

Kim, Lee-Sup; Shin, Wongyu; Moon, Youngsuk; Kwon, Yongkee; Jang, Jaemin

5
Memory device supporting rank-level parallelism and memory system including the same

Kim, Lee-Sup; Shin, Wongyu; Moon, Youngsuk; Kwon, Yongkee; Jang, Jaemin

6
Memory device supporting rank-level parallelism and memory system including the same

Kim, Lee-Sup; Shin, Wongyu; Moon, Youngsuk; Kwon, Yongkee; Jang, Jaemin

7
Multiple Clone Row DRAM: A Low Latency and Area Optimizded DRAM

Choi, Jungwhan; Shin, wongyu; Jang, Jaemin; Suh, Jinwoong; Kwon, Yongkee; Moon, Youngsuk; Kim, Lee-Sup, 2015 ACM/IEEE International Symposium on Computer Architecture, ACM SIGGRAPH and IEEE TCCA, 2015-06-15

8
Multiple clone row DRAM: A low latency and area optimized DRAM

Choi, Jungwhan; Shin, Wongyu; Jang, Jaemin; Suh, Jinwoong; Kwon, Yongkee; Moon, Youngsuk; Kim, Lee-Sup, 42nd Annual International Symposium on Computer Architecture, ISCA 2015, pp.223 - 234, Institute of Electrical and Electronics Engineers Inc., 2015-06

9
Q-DRAM: Quick-Access DRAM with Decoupled Restoring from Row-Activation

Shin, Wongyu; Choi, Jung Whan; Jang, Jaemin; Suh, Jinwoong; Kwon, Yongkee; Moon, Youngsuk; Kim, Hongsik; et al, IEEE TRANSACTIONS ON COMPUTERS, v.65, no.7, pp.2213 - 2227, 2016-07

10
Rank-Level Parallelism in DRAM

Shin, Wongyu; Jang, Jaemin; Choi, Jungwhan; Suh, Jinwoong; Kwon, Yongkee; Moon, Youngsuk; Kim, Lee-Sup, IEEE TRANSACTIONS ON COMPUTERS, v.66, no.7, pp.1274 - 1280, 2017-07

11
Refresh-Aware Write Recovery Memory Controller

Jang, Jaemin; Shin, Wongyu; Choi, Jungwhan; Suh, Jinwoong; Kwon, Yongkee; Kim, Yongju; Kim, Lee-Sup, IEEE TRANSACTIONS ON COMPUTERS, v.66, no.4, pp.688 - 701, 2017-04

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