Memory device supporting rank-level parallelism and memory system including the same랭크 레벨의 병렬화를 지원하는 메모리 장치 및 메모리 시스템

Cited 0 time in webofscience Cited 0 time in scopus
  • Hit : 145
  • Download : 0
A memory system may include: a memory controller; a plurality of ranks; and a rank shared bus configured to couple the memory controller and the plurality of ranks. Each of the plurality of ranks may include: a plurality of banks; a rank bus coupled to the plurality of banks and configured to selectively transmit data to the rank shared bus or an intermediate buffer and selectively receive data from the rank shared bus or the intermediate buffer; and an intermediate buffer configured to be selectively coupled to the rank bus or the rank shared bus, according to a first signal from the memory controller.
Assignee
KAIST, SK Hynix Inc.
Country
US (United States)
Application Date
2019-09-18
Application Number
16574425
Registration Date
2021-09-07
Registration Number
11113211
URI
http://hdl.handle.net/10203/288871
Appears in Collection
EE-Patent(특허)
Files in This Item
There are no files associated with this item.

qr_code

  • mendeley

    citeulike


rss_1.0 rss_2.0 atom_1.0