Browse "College of Engineering(공과대학)" by Type Conference
Showing results 1361 to 1380 of 91054
| A 4-Node Non-conforming Flat Shell Element with Drilling DOF 최창근, Proceedings of COSEIK Symposium-Autumn, 1998 |
| A 4-Node Non-conforming Flat Shell Element with Drilling Drilling DOF Choi, Chang Koon, ASCE Engineering Mechanics Conference, 1999 |
| A 4-to-42V Input, 95.5% Efficiency, 3.2μA-IQ, DC-DC Buck Converter Featuring a Leakage-Emulated Bootstrap Re-fresher and Anti-Deadlock Self-Bias Supply for Battery-Powered Automotive Uses Lee, HeeJun; Han, Hyunki; Kim, Hyun-Sik, 44th Annual IEEE Custom Integrated Circuits Conference, CICC 2023, IEEE, 2023-04-26 |
| A 4.2-pJ/Conv 10-b Asynchronous ADC with Hybrid Two-Tier Level-Crossing Event Coding Kubendran, Rajkumar; Park, Jongkil; Sharma, Ritvik; Kim, Chul; Joshi, Siddharth; Cauwenberghs, Gert; Ha, Sohmyung, 52nd IEEE International Symposium on Circuits and Systems, ISCAS 2020, Institute of Electrical and Electronics Engineers, 2020-10 |
| A 4.2mW 10MHz BW 74.4dB SNDR Fourth-order CT DSM with Second-order Digital Noise Coupling Utilizing an 8b SAR ADC Jang, Il-Hoon; Seo, Min-Jae; Kim, Mi-Young; Lee, Jae-Keun; Baek, Seung-Yeob; Kwon, Sun-Woo; Choi, Michael; et al, Symposium on VLSI Circuits, pp.C34 - C35, IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 2017-06-06 |
| A 4.3 GHz On-Off Mode Optically Controlled Oscillator Using an RTD/HPT Based OEIC Technology with 3 pJ/bit Energy Efficiency Park, Jae Hong; Lee, Ki Won; Lee, Joo Seok; Yang, Kyoung Hoon, IEEE International Conference on InP and Related Materials, IEEE, 2015-06-29 |
| A 4.45 ms Low-Latency 3D Point-Cloud-Based Neural Network Processor for Hand Pose Estimation in Immersive Wearable Devices Im, DongSeok; Yoo, Hoi-Jun; Kang, Sanghoon; Han, Donghyeon; Choi, Sungpill, IEEE Symposium on VLSI Circuits, VLSI Circuits 2020, Institute of Electrical and Electronics Engineers Inc., 2020-06-16 |
| A 4.5V-Input 0.3-to-1.7V-Output Step-Down Always-Dual-Path DC-DC Converter Achieving 91.5%-Efficiency with 250mΩ-DCR Inductor for Low-Voltage SoCs Ko, Jae-Young; Huh, Yeunhee; Ko, Min-Woo; Kang, Gyeong-Gu; Cho, Gyu-Hyeong; Kim, Hyun-Sik, 2021 Symposium on VLSI Circuits, IEEE, 2021-06-13 |
| A 4.75GOPS single-chip programmable processor array consisting of a multithreaded processor and multiple SIMD and IO processors Bae, Y.-D.; Park, In-Cheol, Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, CICC, pp.583 - 586, 2004-10-03 |
| A 4.7MHz 53 mu W Fully Differential CMOS Reference Clock Oscillator with-22dB Worst-Case PSNR for Miniaturized SoCs Lee, Junghyup; Park, Pyoungwon; Cho, Seong-Hwan; Je, Minkyu, 2015 IEEE International Solid- State Circuits Conference, IEEE, 2015-02-23 |
| A 4.8-mW 10Mb/s wideband signaling receiver analog front-end for human body communications Song, Seong-Jun; Cho, Namjun; Kim, Sunyoung; Yoo, Hoi-Jun, ESSCIRC 2006 - 32nd European Solid-State Circuits Conference, pp.488 - 491, ESSCIRC, 2006-09-19 |
| A 4.84mW 30fps Dual Frequency Division Multiplexing Electrical Impedance Tomography SoC for Lung Ventilation Monitoring System Yoo, Hoi-Jun; Lee, Yongsu; Song, Kiseok, IEEE Symposium on VLSI Circuits (VLSI Circuits), pp.C204 - C205, IEEE, 2015-06-18 |
| A 4.86 μW/Channel Fully Differential Multi-Channel Neural Recording System Lee, Taeju; Cha, Ji-Hyoung; Han, Su-Hyun; Kim, Seong-Jin; Je, Minkyu, International SoC Design Conference, pp.68 - 69, IEEE, 2018-11-13 |
| A 4.8pJ/b 56Gb/s ADC-Based PAM-4 Wireline Receiver Data-Path with Cyclic Prefix in 14nm FinFET Kim, Gain; Kull, Lukas; Luu, Danny; Braendli, Matthias; Menolfi, Christian; Francese, Pier-Andrea; Yueksel, Hazar; et al, 15th IEEE Asian Solid-State Circuits Conference, A-SSCC 2019, pp.239 - 240, Institute of Electrical and Electronics Engineers Inc., 2019-11 |
| A 4.9 m Omega-Sensitivity Mobile Electrical Impedance Tomography IC for Early Breast-Cancer Detection System Hong, Sunjoo; Lee, Kwonjoon; Ha, Unsoo; Kim, Hyunki; Lee, Yongsu; Kim, Youchang; Yoo, Hoi-Jun, 2014 IEEE International Solid-State Circuits Conference (ISSCC), IEEE, 2014-02-11 |
| A 4.9mW 270MHz CMOS frequency synthesizer/FSK modulator Choi, H.; Shin, S.; Ku, Y.; Jeong, M.; Lee, Kwyro, 2003 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, pp.443 - 446, IEEE, 2003-06-08 |
| A 4.9mW Neural Network Task Scheduler for Congestion-Minimized Network-on-Chip in Multi-Core Systems Yoo, Hoi-Jun; Kim, Youchang; Kim, Gyeonghoon; Hong, Injoon; Kim, Donghyun, IEEE Asian Solid-State Circuits Conference (A-SSCC), pp.213 - 216, IEEE, 2014-11-12 |
| A 40Gb/s Low DC-power 2:1 Multiplexer IC using a Monolithic quantum-effect device technology Choi, S; Jeong,Y; Lee, J; 양경훈, Korean Conference on Semiconductors, pp.26 - 27, 2009 |
| A 40mV transformer-reuse self-startup boost converter with MPPT control for thermoelectric energy harvesting Im, Jong-Pil; Wang, Se-Won; Lee, Kang-Ho; Woo, Young-Jin; Yuk, Young-Sub; Kong, Tae-Hwang; Hong, Sung-Wan; et al, 2012 IEEE International Solid-State Circuits Conference, ISSCC 2012, pp.104 - 106, IEEE, 2012-02-20 |
| A 40nm CMOS 12b 200MS/s Single-amplifier Dual-residue Pipelined-SAR ADC Seo, Min-Jae; Kim, Ye Dam; Chung, Jae-Hyun; Ryu, Seung-Tak, 39th Symposium on VLSI Technology / 33rd Symposium on VLSI Circuits, pp.C72 - C73, IEEE, 2019-06-11 |
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