A 155-mW 50-mvertices/s graphics processor with fixed-point programmable vertex shader for mobile applications

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A 36 mm(2) graphics processor with fixed-point programmable vertex shader is designed and implemented for portable two-dimensional (2-D) and three-dimensional (3-D) graphics applications. The graphics processor contains an ARM-10 compatible 32-bit RISC processor, a 128-bit programmable fixed-point single-instruction-multiple-data (SIMD) vertex shader, a low-power rendering engine, and a programmable frequency synthesizer (PFS). Different from conventional graphics hardware, the proposed graphics processor implements ARM-10 co-processor architecture with dual operations so that user-programmable vertex shading is possible for advanced graphics algorithms and various streaming multimedia processing in mobile applications. The circuits and architecture of the graphics processor are optimized for fixed-point operations and achieve the low power consumption with help of instruction-level power management of the vertex shader and pixel-level clock gating of the rendering engine. The PFS with a fully balanced voltage-controlled oscillator (VCO) controls the clock frequency from 8 MHz to 271 MHz continuously and adaptively for low-power modes by software. The chip shows 50 Mvertices/s and 200 Mtexels/s peak graphics performance, dissipating 155 mW in 0.18-mu m 6-metal standard CMOS logic process.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2006-05
Language
English
Article Type
Article
Keywords

DECODER; LSI

Citation

IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.41, pp.1081 - 1091

ISSN
0018-9200
DOI
10.1109/JSSC.2006.872869
URI
http://hdl.handle.net/10203/6251
Appears in Collection
EE-Journal Papers(저널논문)
Files in This Item
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