DC Field | Value | Language |
---|---|---|
dc.contributor.author | Sohn, JH | ko |
dc.contributor.author | Woo, JH | ko |
dc.contributor.author | Lee, MW | ko |
dc.contributor.author | Kim, HJ | ko |
dc.contributor.author | Woo, R | ko |
dc.contributor.author | Yoo, Hoi-Jun | ko |
dc.date.accessioned | 2008-07-22T05:07:21Z | - |
dc.date.available | 2008-07-22T05:07:21Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 2006-05 | - |
dc.identifier.citation | IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.41, pp.1081 - 1091 | - |
dc.identifier.issn | 0018-9200 | - |
dc.identifier.uri | http://hdl.handle.net/10203/6251 | - |
dc.description.abstract | A 36 mm(2) graphics processor with fixed-point programmable vertex shader is designed and implemented for portable two-dimensional (2-D) and three-dimensional (3-D) graphics applications. The graphics processor contains an ARM-10 compatible 32-bit RISC processor, a 128-bit programmable fixed-point single-instruction-multiple-data (SIMD) vertex shader, a low-power rendering engine, and a programmable frequency synthesizer (PFS). Different from conventional graphics hardware, the proposed graphics processor implements ARM-10 co-processor architecture with dual operations so that user-programmable vertex shading is possible for advanced graphics algorithms and various streaming multimedia processing in mobile applications. The circuits and architecture of the graphics processor are optimized for fixed-point operations and achieve the low power consumption with help of instruction-level power management of the vertex shader and pixel-level clock gating of the rendering engine. The PFS with a fully balanced voltage-controlled oscillator (VCO) controls the clock frequency from 8 MHz to 271 MHz continuously and adaptively for low-power modes by software. The chip shows 50 Mvertices/s and 200 Mtexels/s peak graphics performance, dissipating 155 mW in 0.18-mu m 6-metal standard CMOS logic process. | - |
dc.language | English | - |
dc.language.iso | en_US | en |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | DECODER | - |
dc.subject | LSI | - |
dc.title | A 155-mW 50-mvertices/s graphics processor with fixed-point programmable vertex shader for mobile applications | - |
dc.type | Article | - |
dc.identifier.wosid | 000237210500009 | - |
dc.identifier.scopusid | 2-s2.0-33646388655 | - |
dc.type.rims | ART | - |
dc.citation.volume | 41 | - |
dc.citation.beginningpage | 1081 | - |
dc.citation.endingpage | 1091 | - |
dc.citation.publicationname | IEEE JOURNAL OF SOLID-STATE CIRCUITS | - |
dc.identifier.doi | 10.1109/JSSC.2006.872869 | - |
dc.contributor.localauthor | Yoo, Hoi-Jun | - |
dc.contributor.nonIdAuthor | Sohn, JH | - |
dc.contributor.nonIdAuthor | Woo, JH | - |
dc.contributor.nonIdAuthor | Lee, MW | - |
dc.contributor.nonIdAuthor | Kim, HJ | - |
dc.contributor.nonIdAuthor | Woo, R | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | ARM co-processor | - |
dc.subject.keywordAuthor | fixed-point system | - |
dc.subject.keywordAuthor | frequency scaling | - |
dc.subject.keywordAuthor | low-power electronics | - |
dc.subject.keywordAuthor | mobile applications | - |
dc.subject.keywordAuthor | programmability | - |
dc.subject.keywordAuthor | rendering engine | - |
dc.subject.keywordAuthor | single-instruction-multiple-data (SIMD) processing | - |
dc.subject.keywordAuthor | three-dimensional graphics | - |
dc.subject.keywordAuthor | vertex shader | - |
dc.subject.keywordPlus | DECODER | - |
dc.subject.keywordPlus | LSI | - |
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