Software-based design and implementation for digital communication systems

Abstract

As the integration technology of System-On-a-Chip (SoC) is being advanced, it becomes possible to satisfy the demands on high-performance or multiple-purpose applications with software implementation. However, for those time-critical applications, a high-speed processor or multiple processors are necessary. In this paper, we design and implement two applications on one or multiple low-speed processors in software. The paper is composed of two parts. The first part is regarding ‘Software-based parallel CRC architecture for multi-process system-on-a-chip’. This part explores applicable CRC architectures for MP SoC in order to implement a high-speed CRC. For MP SoC implementation, we firstly propose a new parallel CRC algorithm which describes how to partition the CRC computation resources according to the number of processors. After that, several communication architectures are suggested through the CRC communication flow analysis. With these architectures, we explore the CRC by using TLM (Transaction Level Model). From the simulation results, we present that the FIFO-based architecture is the most efficient architecture for a high-speed CRC than other architectures. In addition, we prove that the CRC with four processors on a FIFO-based architecture meets the latency requirement of the 802.11a WLAN at the highest data rate, 54Mbps. The second part is concerning ‘Software implementation for multi-protocol 13.56MHz RFID reader’. In this part, we design and implement a multi-protocol 13.56MHz reader in software. In order to satisfy the timing constraint, three level optimization schemes called compile level, syntax level, and architectural level optimization schemes are applied. The execution time of the optimized code is reduced by 85%, so that it fully satisfies the timing constraint at 60MHz EISC core. In addition, the binary code size is minimized up to 211KBytes which is possible to be loaded on the 256KB size memory.