학위논문(박사) - 한국과학기술원 : 신소재공학과, 2011.2, [ viii, 96 p. ]
under bump metallurgy; solder; reliability; wafer level chip size package; dielectric material; 유전재료; 하부금속층; 솔더; 신뢰성; 웨이퍼레벨패키지
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