Browse "EE-Journal Papers(저널논문)" by Title
Showing results 401 to 420 of 14313
| A 40-nm CMOS 12b 120-MS/s Nonbinary SAR-Assisted SAR ADC With Double Clock-Rate Coarse Decision Roh, Yi-Ju; Chang, Dong-Jin; Ryu, Seung-Tak, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.67, no.12, pp.2833 - 2837, 2020-12 |
| A 400-nW 19.5-fJ/Conversion-Step 8-ENOB 80-kS/s SAR ADC in 0.18-um CMOS Cheong, Jia Hao; Chan, Kok Lim; Khannur, Pradeep Basappa; Tiew, Kei Tee; Je, Minkyu, IEEE Transactions on Circuits and Systems II: Express Briefs, v.58, no.7, pp.407 - 411, 2011-07 |
| A 40fJ/c-s 1 V 10 bit SARADC with Dual Sampling Capacitive DAC Topology Kim, Bin-Hee; Yan, Long; Yoo, Jerald; Yoo, Hoi-Jun, JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, v.11, pp.23 - 32, 2011-03 |
| A 43 nW, 32 kHz, +/- 4.2 ppm Piecewise Linear Temperature-Compensated Crystal Oscillator With Delta sigma-Modulated Load Capacitance Park, Sujin; Seol, Ji-Hwan; Xu, Li; Cho, Seonghwan; Sylvester, Dennis; Blaauw, David, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.57, no.4, pp.1175 - 1186, 2022-04 |
| A 43.1TOPS/W Energy-Efficient Absolute-Difference-Accumulation Operation Computing-In-Memory With Computation Reuse Um, Soyeon; Kim, Sangyeob; Kim, Sangjin; Yoo, Hoi-Jun, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.68, no.5, pp.1605 - 1609, 2021-05 |
| A 43.3-mu W Biopotential Amplifier With Tolerance to Common-Mode Interference of 18 V-pp and T-CMRR of 105 dB in 180-nm CMOS Koo, Nahmil; Kim, Hyojun; Cho, Seonghwan, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.58, no.2, pp.508 - 519, 2023-02 |
| A 44.2-TOPS/W CNN Processor With Variation-Tolerant Analog Datapath and Variation Compensating Circuit Seo, Jin-O; Seok, Mingoo; Cho, Seonghwan, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.59, no.5, pp.1603 - 1611, 2024-05 |
| A 45 mu W Injection-Locked FSK Wake-Up Receiver With Frequency-to-Envelope Conversion for Crystal-Less Wireless Body Area Network Bae, Joonsung; Yoo, Hoi-Jun, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.50, no.6, pp.1351 - 1360, 2015-06 |
| A 45-dB, 150-Hz, and 18-mW Touch Controller for On-Cell Capacitive TSP Systems Jang, Yeongshin; Ko, Younghun; Choi, Jung-Min; Oh, Hyoung Seok; Lee, Sang-Gug, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.61, no.10, pp.748 - 752, 2014-10 |
| A 45-mu W, 162.1-dBc/Hz FoM, 490-MHz Two-Stage Differential Ring VCO Without a Cross-Coupled Latch Jung, Ohyong; Seok, HyunGi; Dissanayake, Anjana; Lee, Sang-Gug, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.65, no.11, pp.1579 - 1583, 2018-11 |
| A 457 nW Near-Threshold Cognitive Multi-Functional ECG Processor for Long-Term Cardiac Monitoring Liu, Xin; Zhou, Jun; Yang, Yongkui; Wang, Bo; Lan, Jingjing; Wang, Chao; Luo, Jianwen; et al, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.49, no.11, pp.2422 - 2434, 2014-11 |
| A 46-nF/10-M omega Range 114-aF/0.37-omega Resolution Parasitic- and Temperature-Insensitive Reconfigurable RC-to-Digital Converter in 0.18-mu m CMOS George, Arup K.; Shim, Wooyoon; Kung, Jaeha; Kim, Ji-Hoon; Je, Minkyu; Lee, Junghyup, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.69, no.3, pp.1171 - 1184, 2022-03 |
| A 470-mu W 5-GHz Digitally Controlled Injection-Locked Multi-Modulus Frequency Divider With an In-Phase Dual-Input Injection Scheme Lee, Joonhee; Park, Sunghyun; Cho, SeongHwan, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.19, no.1, pp.61 - 70, 2011-01 |
| A 48 mu W, 8.88 mW/W Batteryless Wirelessly Power Transferred Body Channel Communication Identification System Lee, Jihee; Lee, Yongsu; Cho, Hyunwoo; Yoo, Hoi-Jun, JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, v.17, no.6, pp.927 - 934, 2017-12 |
| A 4800 bps LPC Vocoder with Improved Excitation Un, Chong-Kwan; W.Y.Sung, 한국음향학회지, v.1, no.1, pp.54 - 59, 1982-03 |
| A 49.5 mW Multi-Scale Linear Quantized Online Learning Processor for Real-Time Adaptive Object Detection Song, Seokchan; Kim, Soyeon; Park, Gwangtae; Han, Donghyeon; Yoo, Hoi-Jun, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.69, no.5, pp.2443 - 2447, 2022-05 |
| A 5 Gbps 1.6 mW/G bps/CH Adaptive Crosstalk Cancellation Scheme With Reference-less Digital Calibration and Switched Termination Resistors for Single-Ended Parallel Interface Hwang, Kyu-Dong; Kim, Lee-Sup, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.61, no.10, pp.3016 - 3024, 2014-10 |
| A 5-BIT CMOS PHASE SHIFTER WITH LOW PHASE AND AMPLITUDE ERROR USING A NEW 1800 PHASE SHIFTER FEATURING PROCESS-VARIATION IMMUNITY Kang, Dong-Woo; Hong, Songcheol, MICROWAVE AND OPTICAL TECHNOLOGY LETTERS, v.52, no.6, pp.1325 - 1328, 2010-06 |
| A 5-Gb/s 2.67-mW/Gb/s Digital Clock and Data Recovery With Hybrid Dithering Using a Time-Dithered Delta-Sigma Modulator Lee, Taeho; Kim, Yonghun; Sim, Jaehyeong; Park, Jun-Seok; Kim, Lee-Sup, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.24, no.4, pp.1450 - 1459, 2016-04 |
| A 5-Gb/s Digital Clock and Data Recovery Circuit With Reduced DCO Supply Noise Sensitivity Utilizing Coupling Network Lee, Taeho; Kim, Yong Hun; Kim, Lee-Sup, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.25, no.1, pp.380 - 384, 2017-01 |
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