A 43.1TOPS/W Energy-Efficient Absolute-Difference-Accumulation Operation Computing-In-Memory With Computation Reuse

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Recently, Computing-In-Memory (CIM) processors have been proposed to achieve high energy-efficiency by reducing data movement and solving memory bottlenecks. Furthermore, a network with high accurate image classification has been introduced through the Absolute-Difference-Accumulation (ADA) operation instead of the multiplication-and-accumulation operation, which is widely used in DNN. ADA operation provides not only opportunities for high energy-efficient DNN accelerating by reducing multiplication but also a chance to reuse computation results. However, the previous CIM processor cannot reuse previous computation results for other computations. In this brief, we propose a high accurate and high energy-efficient ADA-CIM processor that with two key features: 1) computation reuse for low-power, resulting in a 49.5% CIM operation power reduction, and 2) low-cost sign prediction core with 3-bit activation and weight quantization for high utilization. From the two key features, the proposed ADA-CIM processor is simulated in 28 nm CMOS technology and occupies 3.78 mm(2). It consumes 2.77mW and achieves 43.1 TOPS/W energy-efficiency with a high-accuracy of 91.62% at CIFAR-10 (ResNet-20).
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2021-05
Language
English
Article Type
Article
Citation

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.68, no.5, pp.1605 - 1609

ISSN
1549-7747
DOI
10.1109/TCSII.2021.3067327
URI
http://hdl.handle.net/10203/285390
Appears in Collection
EE-Journal Papers(저널논문)
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