(A) study on time slot assignment problem for an SS/TDMA system

Abstract

In this thesis, we examine the problem of time-slot assignment in an SS/TDMA system operating in a packet-switched environment. We seek to assing time slots in order to minimize the number of switchings subject to minimize the average packet waiting time. Most of time-slot assignment algorithms developed so far either suffer from the computational burden or provide a solution obtained by ignoring some constraints, for example, the waiting time. So, we present new algorithms, which require much less computational effort and give a good solution. Our algorithm is efficient in the sense that (1) its computational procedure is relatively simple, (2) the resulting SS/TDMA frame utilization is 100 \% for any vraffic matrix, (3) the waiting time between arrival of a packet at a ground station and its transmission, and the number of switching configurations are quite small. Simulation has been performed to support our algorithms. Simulation results show that our algorithms give better performance.