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Results 1-10 of 37 (Search time: 0.005 seconds).
| NO | Title, Author(s) (Publication Title, Volume Issue, Page, Issue Date) |
|---|---|
| Effect of ground guard fence with via and ground slot on radiated emission in multi-layer digital printed circuit board Lee, H.; Kim, J.; Ahn, S.; Byun, J.-G.; Kang, D.-S.; Choi, C.-S.; Hwang, H.-J.; Kim, Joungho, 2001 IEEE International Symposium on Electromagnetic Compatibility, v.1, pp.653 - 656, IEEE, 2001-08-13 | |
| Slot transmission line model of interconnections crossing split power/ground plane on high-speed multi-layer board Kim, Joungho; Kim, H.; Jeong, Y.; Lee, J.; Kim, J., 6th IEEE Workshop on Signal Propagation on Interconnects, SPI, pp.23 - 26, 2002-05-12 | |
| Design guidelines of spread spectrum clock for suppression of radiation and interference from high-speed interconnection line Kim, J.; Jun, P.; Byun, J.-G.; Kim, Joungho, 6th IEEE Workshop on Signal Propagation on Interconnects, SPI, pp.189 - 192, IEEE, 2002-05-12 | |
| Effect of power/ground partitioning and stitching capacitor placement on signal integrity and emi of multi-layer and multi power system Kim, Joungho; Kim, H.; Lee, H.; Kim, J.; Kim, J., Pacific Rim/International, Intersociety Electronic Packaging Technical/Business Conference and Exhibition, v.1, pp.59 - 62, 2001-07-08 | |
| An evaluation of differential impedance in PCBs using two single-ended probes only Kam, D.G.; Lee, H.; Ryu, W.; Kim, J.; Park, B.; Kim, Joungho, 6th IEEE Workshop on Signal Propagation on Interconnects, SPI, pp.169 - 171, IEEE, 2002-05-12 | |
| A chip-package hybrid DLL loop and clock distribution network for low-jitter clock delivery Chung, D.; Ryu, C.; Kim, H.; Lee, C.; Kim, J.; Kim, J.; Bae, K.; Yu, J.; Lee, S.; Yoo, H.; Kim, Joungho, 2005 IEEE International Solid-State Circuits Conference, ISSCC, v.48, pp.514 - 614, 2005-02-06 | |
| Signal quality test with 3-dimensional BER opening for non-coherent Ultra Wide-Band (UWB) System-in-Package (SiP) Yoon, C.; Kim, Joungho; Kim, J., 2009 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2009, 2009-12-02 | |
| Impact of partial EBG PDN on PI, SI and lumped model-based correlation Lee, J.; Lee, H.; Park, K.; Chung, B.; Kim, J.; Kim, Joungho, 2008 Asia-Pacific Symposium on Electromagnetic Compatibility and 19th International Zurich Symposium on Electromagnetic Compatibility, APEMC 2008, pp.168 - 171, 2008-05-19 | |
| Modeling and analysis of die-to-die vertical coupling in 3-D IC Lee, S.; Kim, G.; Kim, J.; Song, T.; Lee, J.; Lee, H.; Park, K.; Kim, Joungho, 2009 11th Electronic Packaging Technology Conference, EPTC 2009, pp.707 - 711, 2009-12-09 | |
| An estimation method of chip level power distribution network inductance using full wave simulation and segmentation method Kim, J.; Shim, J.; Lee, W.; Pak, J.S.; Kim, Joungho, 2008 Asia-Pacific Symposium on Electromagnetic Compatibility and 19th International Zurich Symposium on Electromagnetic Compatibility, APEMC 2008, pp.339 - 342, 2008-05-19 |