Search
Results 1-4 of 4 (Search time: 0.003 seconds).
| NO | Title, Author(s) (Publication Title, Volume Issue, Page, Issue Date) |
|---|---|
| A chip-package hybrid DLL loop and clock distribution network for low-jitter clock delivery Chung, D.; Ryu, C.; Kim, H.; Lee, C.; Kim, J.; Kim, J.; Bae, K.; Yu, J.; Lee, S.; Yoo, H.; Kim, Joungho, 2005 IEEE International Solid-State Circuits Conference, ISSCC, v.48, pp.514 - 614, 2005-02-06 | |
| High frequency electrical circuit model of chip-to-chip vertical via iterconnection for 3-D chip stacking package Ryu, C.; Chung, D.; Lee, J.; Lee, K.; Oh, T.; Kim, Joungho, 14th Topical Meeting on Electrical Performance of Electronic Packaging 2005, v.2005, pp.151 - 154, 2005-10-24 | |
| Near field and far field analysis of Alternating Impedance Electromagnetic Bandgap (AI-EBG) structure for mixed-signal applications Choi, J.; Kam, D.G.; Chung, D.; Srinivasan, K.; Govind, V.; Kim, Joungho; Swaminathan, M., 14th Topical Meeting on Electrical Performance of Electronic Packaging 2005, v.2005, pp.69 - 72, IEEE, 2005-10-24 | |
| Chip-package co-design of power distribution network for system-in-package applications Kim, G.; Kam, D.G.; Chung, D.; Kim, Joungho, 6th Electronics Packaging Technology Conference, EPTC 2004, pp.499 - 501, IEEE, 2005-12-08 |
Discover