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| NO | Title, Author(s) (Publication Title, Volume Issue, Page, Issue Date) |
|---|---|
| Modeling of Through-silicon Via (TSV) with an hmbedded High-density Metal-insulator-metal (MIM) Capacitor Cho, Kyunjun; Kim, Youngwoo; Kim, Subin; Park, Gapyeol; Son, Kyungjune; Park, Hyunwook; Kim, Seongguk; Choi, Sumin; Kim, Dong-Hyun; Kim, Joungho, IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS), IEEE, 2018-12 | |
| Measurement, Simulation and Mathematical Estimation of Magnetic Field Shielding Effectiveness of Sputtered Shielding Materials using Spiral Coils Song, Kyunghwan; Kim, Subin; Jeong, Seungtaek; Kim, Dong-Hyun; Son, Kyungjune; Heo, Jin; Han, Kyumin; Jung, Yusup; Kim, Hongseok; Kim, Joungho, 2018 IEEE Symposium on Electromagnetic Compatibility, Signal & Power Integrity, pp.47 - 51, 2018 IEEE Symposium on Electromagnetic Compatibility, Signal & Power Integrity, 2018-08-01 | |
| Modeling and Signal Integrity Analysis of 3D XPoint Memory Cells and Interconnections with Memory Size Variations During Read Operation Son, Kyungjune; Cho, Kyungjun; Kim, Subin; Park, Gapyeol; Song, Kyunghwan; Kim, Joungho, 2018 IEEE Symposium on Electromagnetic Compatibility, Signal & Power Integrity, pp.223 - 227, 2018 IEEE Symposium on Electromagnetic Compatibility, Signal & Power Integrity, 2018-08-01 | |
| Signal and Power Integrity (SI/PI) Analysis of Heterogeneous Integration Using Embedded Multi-die Interconnect Bridge (EMIB) Technology for High Bandwidth Memory (HBM) Kim, Joungho; Cho, Kyungjun; Lee, Hyunsuk; Park, Gapyeol; Kim, Subin; Son, Kyungjune; Choi, Sumin, 2017 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS), 2017 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS), 2017-12-16 | |
| Modeling and verification of 3-dimensional resistive storage class memory with high speed circuits for core operation Son, Kyungjune; Cho, Kyungjun; Kim, Subin; Park, Shinyoung; Park, Gap Yeol; Kim, Seongguk; Shin, Taein; Kim, Joungho, 2019 IEEE Asia-Pacific Microwave Conference, APMC 2019, pp.694 - 696, Institute of Electrical and Electronics Engineers Inc., 2019-12 | |
| Bayesian Optimization of High-Speed Channel for Signal Integrity Analysis Lho, Daehwan; Park, Junyong; Park, Hyunwook; Park, Shinyoung; Kim, SeongGuk; Kang, Hyungmin; Kim, Subin; Park, Gap Yeol; Son, Kyungjune; Kim, Joungho, 28th IEEE Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2019, Institute of Electrical and Electronics Engineers Inc., 2019-10 | |
| Power integrity comparison of off-chip, on-interposer, on-chip voltage regulators in 2.5D/3D ICs Kim, Subin; Cho, Kyungjun; Park, Shinyoung; Park, Hyunwook; Kim, Seongguk; Jeong, Seungtaek; Son, Kyungjune; Kim, Joungho, 2019 Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2019, Institute of Electrical and Electronics Engineers Inc., 2019-12 | |
| Impact of On-Chip Interconnection in a Large-Scale Memristor Crossbar Array for Neural Network Accelerator and Neuromorphic Chip Shin, TaeIn; Son, Kyungjune; Kim, Seongguk; Cho, Kyungjun; Park, Shinyoung; Kim, Subin; Park, Gapyeol; Sim, Boogyo; Kim, Joungho, 28th IEEE Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2019, Institute of Electrical and Electronics Engineers Inc., 2019-10 | |
| Modeling and analysis of multiple coupled through-silicon vias (TSVs) for 2.5-D/3-D ICs Cho, Kyungjun; Kim, Youngwoo; Park, Junyong; Kim, Hyesoo; Kim, Seongguk; Kim, Subin; Park, Gap Yeol; Son, Kyungjune; Kim, Joungho, Joint International Symposium on Electromagnetic Compatibility, Sapporo and Asia-Pacific International Symposium on Electromagnetic Compatibility, EMC Sapporo/APEMC 2019, pp.346 - 349, Institute of Electrical and Electronics Engineers Inc., 2019-06 |
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