MOS logic network simulation with a swithch-level model

Abstract

Recently, switch-level model emerges to describe the logical behavior of digital integrated circuits implemented by MOS technology. Since in the switch-level model MOS transisters are primitive elements which consist of logic networks, a simulator which has switch-level model as its basis shows generality and accuracy in simulating MOS logic networks. In this thesis, a switch-level model of MOS logic networks is presented, which can cover almost all MOS structures. A switch-level logic simulator named KAISIM based on this model is developed. Some example circuits are simulated with KAISIM, which show accurate results.