Design of MOS operational amplifiers and modelling of switches in switched capacitor filters

Abstract

Internally compensated operational amplifiers have been designed for the purpose of a switched capacitor filter application assuming a standard n-channel silicon-gate enhancement/depletion MOS process. Specifications of one of the designed operational amplifiers are: open-loop gain=1,100, power consumption=20 mW, commonmode rejection ratio=60 dB, slew rate=1.2 V/uS, unity-gain bandwidth=340 KHz and phase margin=85.5$^\circ$. Those of the other are: open-loop gain=1,300, power consumption=30 mW, slew rate=2.1 V/uS, unity-gain bandwidth=880 KHz and phase margin=65$^\circ$, and common-mode rejection ratio=60 dB. As a preliminary study of complete integration of switched capacitor filters, modelling the MOSFET as a switch is considered. Experimental results for specially designed integrated MOS test chips, are used to determine a reasonable model of the MOSFET as a switch.