(An) intermingle approach to low-density parity-check decoder design supporting fully overlapped operations

Abstract

A new scheduling scheme to improve the resource utilization of a low-density parity-check decoder has been proposed in this thesis. In the proposed scheme, a completely overlapped processing of check nodes and variable nodes is ensured to achieve full utilization of resources, increasing the throughput of the decoder and reducing the overall decoding latency. Moreover, no restriction is posed on the formation of the parity check matrix and any preprocessing is also not required prior to the decoding. The effectiveness of the proposed scheme is measured through a series of simulations using WiMax802.16e codes with considering an additive white Gaussian noise channel. Furthermore, the proposed scheme is used to implement a decoder for a (576, 7, 6) irregular code. Altera’s CycloneII FPGA is used to verify the working of the developed decoder.