(An) area efficient asynchronous gated-ring oscillator time-to-digital converter면적효율을 증가시킨 비동기식 게이티드링 오실레이터 시간-디지털 변환기

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Analog phase locked loops (APLLs) are widely used in area such as clock recovery and frequency synthesis. However, as the process technology has advanced, design of APLLs becomes difficulty in deep-sub micron environment. All-digital PLLs (ADPLLs) solve the problems of APLLs in deep-sub micron environment. Because full-swing digital codes are used, the design in noisy SoC environment is easy. And the passive elements are not used. Because only standard-cells are used, re-design is easy in the new technology. In the ADPLLs, phase-frequency detector (PFD) and charge-pump (CP) are replaced by time-to-digital converter (TDC). And the voltage-controlled oscillator (VCO) is replaced by digitally-controlled oscillator (DCO). The quantization noise from TDC and DCO is generated and degrades the phase noise characteristic of output in ADPLL. That is, the advance of TDC and DCO is issue in the performance of ADPLL. This thesis focuses on the TDC. Gated-ring oscillator (GRO)-TDC is similar to the structure of the VCO-quantizer in the analog-digital converter (ADC) application, except for using the GRO instead of the VCO. The GRO-TDC is configured to ring type, and can be easily designed. Because the outputs of counter are binary code, additional encoder is not required. The main property of the GRO-TDC is intrinsic first-order noise shaping. The quantization noise from resolution limit of GRO is noise-shaped and the in-band noise is reduced. At the result, the effective resolution is increased, and the phase noise of ADPLL is advanced. The proposed structure in this thesis is based on conventional GRO-TDC. The proposed asynchronous GRO-TDC has less area and power consumption, better noise characteristic than conventional GRO-TDC. In the proposed structure, to reduce the gate count of total adders, asynchronous counter is used. And to eliminate the unnecessary adding operation in the conventional structure, adders are isolated to counters by CNT registers. At th...
Advisors
Kim, Lee-Supresearcher김이섭researcher
Description
한국과학기술원 : 전기및전자공학전공,
Publisher
한국과학기술원
Issue Date
2009
Identifier
308876/325007  / 020073639
Language
eng
Description

학위논문(석사) - 한국과학기술원 : 전기및전자공학전공, 2009.2, [ vi, 64 p. ]

Keywords

gated-ring,oscillator; GRO; time-to-digital,converter; TDC; ADPLL; 게이티드링,오실레이터; 시간-디지털,변환기; gated-ring,oscillator; GRO; time-to-digital,converter; TDC; ADPLL; 게이티드링,오실레이터; 시간-디지털,변환기

URI
http://hdl.handle.net/10203/38755
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=308876&flag=dissertation
Appears in Collection
EE-Theses_Master(석사논문)
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