(A) data pattern-tolerant adaptive equalizer using spectrum balancing method

Abstract

As the transmission speed increases in data communication systems, the non-ideal effects of the channel severely degrades the quality of signal. To reduce the bit error rate, equalization is used to compensate the loss of channel. Several methods to realize equalizer have been proposed. However, there are some disadvantages for the each equalizer. To solve the problems of the previous works, a data pattern-tolerant adaptive equalizer using spectrum balancing method is proposed. By adopting spectrum balancing method, problem of imbalanced swing is eliminated. In addition to the high-frequency boosting control loop, this structure has a corner-frequency control loop to guarantee its adaptation accuracy in various data. By controlling the corner-frequency of the RC filters, an adaptive operation with respect to data patterns and data rates is available. By simulation and experiment, data pattern-tolerant and data rate-tolerant operations are proved. The results show that eye opening is enlarged and then bit error rate is reduced in the proposed structure. All the simulation and chip fabrication are based on the 0.18μm CMOS process. The tested maximum operating data rate is 6.4Gb/s and the power dissipation in equalizer core is 85mW. The chip area of equalizer core is 630μmx550μm.