Investigation on Schottky barrier MOSFET for 3D memory application

Abstract

The fabrication and investigation of Schottky barrier MOSFETs (SB-MOSFETs) are presented. It shows good characteristics and compatibility in CMOS technology. To figure out the carrier transport mechanism, newly developed extraction method of effective barrier height is proposed. It shows that the dominant carrier transport is changed corresponding to gate and drain bias condition. The memory application, especially capacitorless DRAM, is also presented. In order to form low barrier height in the source, dopant segregation method at the junction edge is used in memory application. The memory characteristics show good property and the same class with conventional capacitorless DRAM. When device is down scaling, the capacitorless DRAM should be required with high immunity of short channel effect. Therefore, the Schottky barrier MOSFETs are the best candidate for high performance device and memory application. Finally, 3D FinFET by using Schottky source/drain are fabricated, and the 3D memory device application by using Schottky contact remains as further works.