Minimizing leakage power in sequential circuits by using mixed $V_t$ Flip-Flops

Abstract

Dual $V_t$ has been widely used to control leakage, while, at the same time, satisfying circuit performance. However, current approaches target the combinational circuits even though sequential elements, such as flip-flops and latches, contribute an appreciable proportion of the total leakage. The use of dual $V_t$ flip-flops is limited to circuits of large timing slack, because introducing high $V_t$ flip-flops in place of low $V_t$ ones yields abrupt change in timing. We propose mixed $V_t$ flip-flops, which are designed by using both low and high $V_t$, but in different transistors. Compared to low $V_t$ flip-flop, the mixed $V_t$ flip-flops exhibit increased delay, but either on setup time or on clock-to-Q delay but not on both, while their leakage is greatly reduced. We propose a sensitivity-based mixed $V_t$ allocation algorithm to incorporate mixed $V_t$ flip-flops together with dual $V_t$ combinational gates. Experimental results show that an average leakage saving of 43% is achieved, compared to the use of dual $V_t$ on combinational subcircuits alone. The leakage of the flip-flops is cut by 64% on average. We also show how to extend our methodology when three $V_t$ s are utilized.