DC Field | Value | Language |
---|---|---|
dc.contributor.advisor | Shin, Young-soo | - |
dc.contributor.advisor | 신영수 | - |
dc.contributor.author | Kim, Jae-Hyun | - |
dc.contributor.author | 김재현 | - |
dc.date.accessioned | 2011-12-14T02:05:20Z | - |
dc.date.available | 2011-12-14T02:05:20Z | - |
dc.date.issued | 2008 | - |
dc.identifier.uri | http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=297161&flag=dissertation | - |
dc.identifier.uri | http://hdl.handle.net/10203/38544 | - |
dc.description | 학위논문(석사) - 한국과학기술원 : 전기및전자공학전공, 2008.2, [ viii, 53 p. ] | - |
dc.description.abstract | Dual $V_t$ has been widely used to control leakage, while, at the same time, satisfying circuit performance. However, current approaches target the combinational circuits even though sequential elements, such as flip-flops and latches, contribute an appreciable proportion of the total leakage. The use of dual $V_t$ flip-flops is limited to circuits of large timing slack, because introducing high $V_t$ flip-flops in place of low $V_t$ ones yields abrupt change in timing. We propose mixed $V_t$ flip-flops, which are designed by using both low and high $V_t$, but in different transistors. Compared to low $V_t$ flip-flop, the mixed $V_t$ flip-flops exhibit increased delay, but either on setup time or on clock-to-Q delay but not on both, while their leakage is greatly reduced. We propose a sensitivity-based mixed $V_t$ allocation algorithm to incorporate mixed $V_t$ flip-flops together with dual $V_t$ combinational gates. Experimental results show that an average leakage saving of 43% is achieved, compared to the use of dual $V_t$ on combinational subcircuits alone. The leakage of the flip-flops is cut by 64% on average. We also show how to extend our methodology when three $V_t$ s are utilized. | eng |
dc.language | eng | - |
dc.publisher | 한국과학기술원 | - |
dc.subject | mixed Vt | - |
dc.subject | flip-flop | - |
dc.subject | leakage | - |
dc.subject | sequential | - |
dc.subject | dual Vt | - |
dc.subject | 혼합 문턱전압 | - |
dc.subject | 플립플랍 | - |
dc.subject | 누설전류 | - |
dc.subject | 순차회로 | - |
dc.subject | 두개의 문턱전압 | - |
dc.subject | mixed Vt | - |
dc.subject | flip-flop | - |
dc.subject | leakage | - |
dc.subject | sequential | - |
dc.subject | dual Vt | - |
dc.subject | 혼합 문턱전압 | - |
dc.subject | 플립플랍 | - |
dc.subject | 누설전류 | - |
dc.subject | 순차회로 | - |
dc.subject | 두개의 문턱전압 | - |
dc.title | Minimizing leakage power in sequential circuits by using mixed $V_t$ Flip-Flops | - |
dc.title.alternative | 혼합 문턱전압 플립플랍을 이용한 순차 회로의 누설 전류 감소 기법 | - |
dc.type | Thesis(Master) | - |
dc.identifier.CNRN | 297161/325007 | - |
dc.description.department | 한국과학기술원 : 전기및전자공학전공, | - |
dc.identifier.uid | 020063111 | - |
dc.contributor.localauthor | Shin, Young-soo | - |
dc.contributor.localauthor | 신영수 | - |
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