Multi-embedded-processor architecture for stream processing using smart buffers

Abstract

Stream processing is becoming increasingly important with a wide variety of applications ranging from mobile devices to high-definition interactive television. Stream processing involves capture, storage, manipulation and transmission of stream data such as 2-D graphics, network packets, audio objects, and full-motion video. In order to meet the various requirements on the stream processing applications, a flexible and yet powerful solution based on the embedded processor architecture is presented. The key motivation is reuse of existing general-purpose processor platform. To enhance the stream processing capabilities without modifications on the internal processor cores, a processor connection scheme and a smart buffer structure are proposed. A serial connection of multiple processors increases overall throughput with minimum global wire connections. Due to the producer-consumer locality of stream processing this topology can be applied to most of the stream processing applications. The proposed architecture provides data relay to support applications with complex data flow. The serial connection and kernel locality of stream processing also provides a programmer with easy-to-develop solution without introducing any new programming models and compiler techniques. A smart buffer provides various memory addressing modes supporting various data types required in the stream processing. The internal address generation logic of the smart buffer mitigates the processor’s burden of memory address calculation. The simulation result shows that the proposed buffer structure reduces instruction count by four processor instructions in accessing memory compared to the conventional structure. The proposed architecture is implemented in a 0.18{\mu}m CMOS technology. This processor operates at the maximum frequency of 200MHz with four processing cores included.