Design of low noise readout circuit for capacitive infrared detector

Abstract

In this thesis, the readout circuit for capacitive infrared detector is proposed. The most important requirements of readout circuit are low noise characteristic and high signal to noise ratio(SNR) not to restrict the performance of detectors. The integration method is used to conventional readout circuits for infrared detectors, storing the charges into the integration capacitor for a time to increase the SNR. However, in spite of the merits, integration method is not acceptable due to very large integration capacitance and narrow noise bandwidth hence integration is meaningless. To solve the problems, non integration method like source follower is proposed for the readout circuit of capacitive infrared detector. Because no current flows from the capacitive detector for dc bias, the method which the voltage variation of sensor is directly transferred to the next stage is used. The most dominant noise is the low frequency noise component such as kT/C noise due to the small capacitance, 16~6fF. To reduce the low frequency noise, CDS(Correlated Double Sampling) technique is adopted. By CDS circuit, the rms noise voltage of proposed circuit is reduced from 30% to 55%. The NETD(Noise Equivalent Temperature Difference) of fabricated capacitive detector is 20.9mk and when CDS circuit is added the NETD of proposed circuit for 16fF is 5.2mK then the NETD of the overall system is 21.5mK. The difference of NETD between detector and total system is only 0.6mK. This result is satisfied with the condition that the readout circuit should not limit the performance of detector. Designed circuit is fabricated by Hynix/Magnachip 0.35㎛, 2 poly, 4 metal standard CMOS process.