Design of two-stage equalizer for over Gbps signaling on high loss channel

Abstract

Nowadays, data transmission becomes faster and more serialized. Data rate of serial interface is up to several Gbps. High-speed signal suffers from frequency dependent loss which is more severe on higher frequency, when high speed signal transmits on physical channel. Since suffered signal is distorted and causes inter-symbol interference (ISI), receiver cannot recover original data. Frequency dependent loss brings limitation in transmission speed and length of channel. To overcome these limits, several equalization methods are proposed. Compensation loss at half-symbol frequency is typical index of equalizer. Higher compensation loss means not only higher data rate but also longer length of channel. For high loss channel, typical equalizer compensates channel loss in transmitter and receiver. However, it is a possible only in transceiver design. When scope of design is restricted within receiver, it is not enough for typical receiver equalizer to compensate all loss of channel. This paper presents a two-stage receiver equalizer for over Gbps signaling on high loss channel. The two-stage equalizer employs second-order transconductance filter and 4-tap finite-duration impulse response (FIR) filter. Internal clock or phase locked loop (PLL) is not necessary to the proposed equalizer. The proposed equalizer is able to compensate high loss efficiently because the first stage boosts high frequency and the second stage attenuates low frequency. This paper also presents design methods for proposed equalizer and verification of performance of the proposed design by frequency domain and time domain simulations. Finally, the proposed equalizer has been implemented in 0.18-um CMOS technology.