(An) efficient texture cache for programmable vertex shadersVertex shader를 지원하기 위한 효과적인 텍스쳐 캐쉬 설계

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Texture mapping has been widely used to provide realistic looking surfaces of a 3D object by mapping images onto the object``s surfaces. Texture mapping is processed in rasterization stage of the graphics pipeline, and textures are referenced with texture coordinates calculated for every pixel. Texture mapping was the only way for graphics hardware to access the external memory. Texture cache was invented to solve the memory bandwidth problem caused by frequent access of texture. The premise of texture cache is high locality of reference of texture. Vertex texture mapping is new functionality of graphics hardware introduced by recent industrial standards. Vertex texture mapping enables vertex shader in geometry stage of the graphics pipeline to access textures in the external memory. Vertex shader becomes able to manipulate 3D object``s geometry using vertex texture, and to use the calculation results of pixel shader transferred via vertex texture. Bandwidth problem added by vertex texture mapping should be handled with consideration of characteristics of locality in referencing vertex texture. Locality of reference of vertex texture varies depending upon the distribution of vertices. Thus, the conventional cache is not applicable to efficiently support vertex texture mapping. In this paper, a cache for vertex texture is proposed. The proposed cache estimates the amount of locality of texture access and adaptively adjusts the cache operation modes. The estimation of locality is achieved by monitoring the distance between consecutively requested texture pixels (texels) and counting the number of requested texels in a same block. All texels in a block are loaded to the proposed cache in regions of high locality while only requested texels are read without caching in regions of low locality. The proposed cache is implemented using Verilog-HDL and simulated with various patterns of vertex texture access. The proposed cache improves 27.0% of average access cycles co...
Advisors
Kim, Lee-Supresearcher김이섭researcher
Description
한국과학기술원 : 전기및전자공학전공,
Publisher
한국과학기술원
Issue Date
2006
Identifier
255565/325007  / 020043578
Language
eng
Description

학위논문(석사) - 한국과학기술원 : 전기및전자공학전공, 2006.2, [ v, 46 p. ]

Keywords

Texture Cache; 3D Graphics; 3D 그래픽스; 텍스쳐 캐쉬

URI
http://hdl.handle.net/10203/38396
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=255565&flag=dissertation
Appears in Collection
EE-Theses_Master(석사논문)
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