SSN reduction method in high-speed CMOS circuits

Abstract

Simultaneous switching noise (also known as Ground bounce or Delta-I noise) is a voltage glitch induced at power/ground distribution connections due to switching current passing through the wire inductance (L) associated with power or ground rails. In the past, the research on SSN was focused at the I/O buffer, since the large SSN enough to cause the malfunction of the circuits was mostly induced at the I/O buffer. However, SSN in the internal core logic circuitry has become an increasingly larger problem because of millions of transistor contained in it. Also, lower supply voltage reduces noise immunity and threshold voltage, and thus creates greater noise sensitivity. Higher operating frequencies and short rise/fall signal transition time results in higher values of dI/dt. There have been various researches on internal SSN, but most of them were about estimation or modeling the SSN problem, shortly speaking, with CAD perspective. And it was rarely researched with circuit perspective. In this thesis, various SSN reduction methods with the circuit perspective are presented with an array multiplier as a test application. The key concept of the SSN reduction methods is the current waveform modification and selective grouping of the current spikes. It is proved that the proposed SSN reduction methods show the better performance in both reducing the SSN and decreasing the delay. The proposed SSN reduction methods can be used in various mixed IC area.