(A) new path metric memory management to reduce the interconnection area of viterbi decoder

Abstract

In digital communication, error occurrence is inevitable problem. Thus error-correcting coding is an essential technique in data transmission. Convolutional code, one of the most popular error correcting codes is widely used in personal communication system. The Viterbi algorithm, which is a decoding algorithm of convolutional code, is discovered and analyzed by Viterbi in 1967. As personal communication systems are more and more widely used, the power and area of a Viterbi decoder become very important factors. In 1993, an area-efficient scheme that has fewer ACS units than the number of the states has been proposed. In that scheme, a major problem was complex interconnection between ACS units and local path metric memories. For the interconnection, a dynamic network or a set of multiplexers, which requires very large area were used. In this thesis, we propose a state-grouping technique and swapped updating technique to simplify the interconnection. Using these techniques, we can implement the interconnection network of the area-efficient Viterbi decoder with eight simple switching elements. Thus the area of an interconnection network of the decoder is reduced significantly. For comparison, various decoders are implemented and synthesized with anam 0.25㎛ library. As a result, we can save gate counts of interconnection network by 96% compared with gate counts of a decoder using multiplexers.