(A) low power variable length decoder for MPEG-2 based on caching

Abstract

The increased demand for portable multimedia systems has made power an important factor during design process. Though variable length coding / decoding is widely used technique in digital video systems, previous approaches to reduce power consumption have concentrated on other steps such as the discrete cosine transform. In the case of variable length decoder, it has been designed to achieve high throughput. To minimize the total power consumption of entire systems, low power designs are required for all steps including variable-length decoding. In this thesis, a low power variable length decoding architecture exploiting codeword statistics as well as correlation is presented. This approach uses a small lookup table to reduce number of operations in VLC detector where the most of power is consumed. Power consumption is estimated by PowerMill using 0.35um cell library. The simulation result shows that average 35 percent of power reduction is possible compared to previous table partitioning scheme.