(A) 16 × 16-bit Splittable MAC unit for multimedia signal processing

Abstract

A MAC unit is the heart of the multimedia signal processing system. Recently introduced multimedia signal processing DSPs have SIMD instructions and process various data formats. Therefore, a new architecture of the MAC unit which is efficient to perform multimedia signal processing and SIMD instructions is demanded. This thesis describes a 16×16-bit Splittable (SPT) MAC unit for supporting SIMD instructions and multimedia applications. A proposed MAC unit performs one 16×16-bit, two 8×8-bit multiplication-and-accumulations selectively. In addition, the SPT MAC unit performs simultaneous signed and unsigned operations. The SPT MAC unit consists of an array multiplier block, a partial sum adder, and a final parallel adder. An array multiplier block consists of four proposed 8-bit Two-Folded Two-Mode (TFTM) Carry Save Array Multipliers (CSAM) for simultaneous signed and unsigned operations. For fast multiplication, parallelism is used in the TFTM-CSAM. The SPT MAC unit is designed based on latch-styled pipeline using both positive and negative clock period for low latency. The proposed SPT MAC unit is fabricated using 0.25-um 5-metal CMOS technology. Core size is 610×560 $um^{2}$, operating frequency is 100MHz at 2.5V. The bottleneck of the performance is occurred at an array multiplier block. For higher performance, a 2-stage pipelined TFTM-CSAM is proposed. Totally a 4-stage pipelined SPT MAC unit is designed using 2-stage pipelined TFTM-CSAMs. Consequently latency is 2 and operating frequency is 200MHz. The most important factor is that the use of 8-bit data allows twice the parallelism compared to the use of 16-bit data.