Circuits and methods to suppress on-chip power supply noise칩 내부 전원선 잡음 제거를 위한 회로 및 기법에 관한 연구

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Power supply noise is one of the major noise sources causing degradation of circuit performance. As CMOS technology has scaled down, on-chip supply voltage have dropped to about 1V. Allowable power supply fluctuation on power supply line has become extremely lowered to maintain fixed percentage noise budget. The solutions of power supply noise have been developed and the different solutions are applied to core blocks and I/O circuits in system. In Single ended I/O circuits of memory interface, the large signal current variation induced by simultaneous switching of output drivers generates inductive noise on power supply line. This Simultaneous Switching Noise (SSN) is the one of the most serious factors that limits the speed. Although several methods have been proposed, there are some disadvantages for the each method. Directly lowering the slew rate of signal current can reduce SSN. But it results in reduced data eye opening. The second method was multi-level encoding with balancing I/O current. However this method is hard to implementation due to noise margin degradation or encoding/ decoding complexity. Another method is DBI-DC data bus inversion coding that is applied to GDDR4 (Graphic Double Data Rate) SDRAM. This method reduces the maximum current variation to half and reduces SSN noise to about half theoretically. However more effective solution is required to further reduce SSN than DBI-DC to increase speed. The proposed SSN compensator is auxiliary block to compensate SSN and reduces current variation by pushing additional current to power line. Proposed compensation scheme eliminate the trade-off relation of slew rate and signal integrity and transmitted data is not encoded. This SSN compensation scheme can be employed to any Pseudo Open Drain Logic (PODL) signaling system and applied together other encoding scheme. To see the effect of the proposed SSN compensator, 5Gbps transmitter and receiver frontend blocks are implemented in 0.13um CMOS ...
Advisors
Kim, Lee-Supresearcher김이섭researcher
Description
한국과학기술원 : 전기 및 전자공학과,
Publisher
한국과학기술원
Issue Date
2010
Identifier
419238/325007  / 020083496
Language
eng
Description

학위논문(석사) - 한국과학기술원 : 전기 및 전자공학과, 2010.2, [ vii, 71 p. ]

Keywords

SSN; power supply noise; regulator; 레귤레이터; SSN; 전원선 잡음

URI
http://hdl.handle.net/10203/36629
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=419238&flag=dissertation
Appears in Collection
EE-Theses_Master(석사논문)
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