Scalable modeling of a through silicon via (TSV) channel & proposal of the TSV equalizers in 3D IC집적화된 3차원 IC에서의 관통 실리콘 비아 채널의 모델링 및 이퀄라이져에 관한 연구

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3-dimensional Integrated Circuit (3D IC) is a 3-dimensional integration of the homo or heterogeneous chips such as memory, logic, RF, analog and sensors. It realizes highly dense packaging and high performance due to smaller form factor and reduced interconnect length by vertical integration. As one of the key technology to provide vertical interconnection method, Through Silicon Via (TSV) enables to 3-dimensionally integrate the system. By using structural dimensions of a TSV structure, the scalable model which can be expanded with structural or dimensional change is proposed and verified by measurement. In addition, with the proposed scalable model, we analyzed the electrical characteristics of TSV channel depending on design parameters. With the analysis of the TSV channel, we proposed novel TSV Equalizer which can compensate the frequency dependent loss of a TSV for high speed signal transmission.
Advisors
Kim, Joung-Horesearcher김정호researcher
Description
한국과학기술원 : 전기 및 전자공학과,
Publisher
한국과학기술원
Issue Date
2010
Identifier
419186/325007  / 020083142
Language
eng
Description

학위논문(석사) - 한국과학기술원 : 전기 및 전자공학과, 2010.2, [ ix, 74, 12 p. ]

Keywords

Equalizer; Scalable Model; Through Silicon Via (TSV); 3D IC; 삼차원 집적회로; 이퀄라이져; 확장가능한 모델; 관통 실리콘 비아

URI
http://hdl.handle.net/10203/36603
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=419186&flag=dissertation
Appears in Collection
EE-Theses_Master(석사논문)
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