(A) study on the acceleration schemes of 3-D computer graphics3 차원 컴퓨터 그래픽의 가속방안에 관한 연구

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This thesis includes several acceleration schemes of computer graphics consisting of three parts. The first part introduces a new hardware architecture for 2-D geometry generation and processing applicable to image processing (noise suppression, notch elimination, and contour extraction), graphics processing (polygon scan conversion and multiwindowing with nonrectangular window), and VLSI layout verification (design rule checking). In the second part, Shading Engine, a special purpose hardware architecture for fast image rendering is described. The Shading Engine performs, in a pipeline fashion, the linear interpolation of the Z-depth values as well as the intensities, given those values at the extreme points of each span in the scanline command. It consists of a binary tree interpolator being fed by the two function values at the extreme points of the scanline produced by the two extrapolators connected in cascade. Finally, in the third part, a software algorithm for the fast shadow testing during ray tracing, called Hybrid Shadow Testing scheme (HST), is introduced. In the HST scheme, one of the four subschemes such as Sustain``, ``Self-shadow``, ``Shadow volume scheme``, and ``Conventional scheme`` is selected such that the shadow testing cost is minimized with the result of approximately 50% reduction of the shadow testing time compared to that of the conventional scheme.
Advisors
Kyung, Chong-Minresearcher경종민researcher
Description
한국과학기술원 : 전기 및 전자공학과,
Publisher
한국과학기술원
Issue Date
1989
Identifier
61401/325007 / 000825171
Language
eng
Description

학위논문(박사) - 한국과학기술원 : 전기 및 전자공학과, 1989.2, [ [iv], 100 p. ]

URI
http://hdl.handle.net/10203/36103
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=61401&flag=dissertation
Appears in Collection
EE-Theses_Ph.D.(박사논문)
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