(A) study on the acceleration schemes of 3-D computer graphics

Abstract

This thesis includes several acceleration schemes of computer graphics consisting of three parts. The first part introduces a new hardware architecture for 2-D geometry generation and processing applicable to image processing (noise suppression, notch elimination, and contour extraction), graphics processing (polygon scan conversion and multiwindowing with nonrectangular window), and VLSI layout verification (design rule checking). In the second part, Shading Engine, a special purpose hardware architecture for fast image rendering is described. The Shading Engine performs, in a pipeline fashion, the linear interpolation of the Z-depth values as well as the intensities, given those values at the extreme points of each span in the scanline command. It consists of a binary tree interpolator being fed by the two function values at the extreme points of the scanline produced by the two extrapolators connected in cascade. Finally, in the third part, a software algorithm for the fast shadow testing during ray tracing, called Hybrid Shadow Testing scheme (HST), is introduced. In the HST scheme, one of the four subschemes such as Sustain``, ``Self-shadow``, ``Shadow volume scheme``, and ``Conventional scheme`` is selected such that the shadow testing cost is minimized with the result of approximately 50% reduction of the shadow testing time compared to that of the conventional scheme.