Low cost 3D graphics rasterization algorithms and their hardware implementation

Abstract

In this thesis, 3D graphics rasterization algorithms to reduce hardware area are presented. The proposed pixel traversal algorithm is based on edge function characteristics instead of the intersection test of polygon edges and pixel stamp edge segments. It reduces not only the edge function probe points at the four corners of the pixel stamp, but also one context save-point. Perspective-correct texturing for correct 3D graphics images requires the per-pixel division, but the division can be avoided by midpoint algorithms. For fraction part of texture coordinates to be used in texture filtering, the proposed modified algorithm which separates the evaluation of integer part and the computation of fraction parts. The hardware architecture of the two proposed algorithms is also presented and compared with conventional architecture in the point of area. From primitive and low-level target application to high-end specification applications, the area is reduced by 14.4%~45.8%. The rasterizer of the proposed architecture with four parallel pixel processing units was implemented in a 3D graphics SoC. The SoC contains 17.9M transistors in $50mm^2$ area fabricated in 0.13um 7M CMOS. The SoC operates at 166MHz clock frequency, and the implemented rasterizer achieves a throughput of 666M pixels and 1.3G texture coordinates per second. The implemented SoC is successfully demonstrated on the evaluation board running real-time applications.