The market for digital radio frequency personal communication devices is rapidly expanding with the development of new services and applications as well as adaptability to multiple wireless communication standards. This dissertation shows that oversampled sigma-delta modulators are uniquely suited to channel select filtering for multi-standard capability. It proposes a new concept of sigma-delta modulator structure, named hybrid integrator, and a new method of overload detection, named overload estimator, for resolving critical problems such as overloading, saturation, and non-linearity of internal multi-bit DAC. These proposed schemes can be adapted to some topologies of sigma-delta modulator. The performances of the new architectures are better than those of the conventional architectures. Furthermore, they can make higher order single stage multi-bit sigma-delta modulator be possible with minimum performance degradation. Two implementation examples are provided. And especially, this dissertation intensively analyzes the circuit imperfections according to a finite op-amp DC gain and capacitor mismatches, which are very important factors into digital compensation methods.
In this dissertation, an adaptive clock recovery, which is employs a dual-loop digital PLL (DPLL), is designed for both fast acquisition of input frequency and phase in the short initial preamble period and substantial jitter reduction in the steady-state in wireless communication applications. And a bandwidth adjusting (adaptive) algorithm is presented, which allow both fast acquisition and significant jitter reduction for each different noise environment and hardware requirement. This algorithm, based on the recursive least squares (RLS) criterion, suggest an optimal sequence of control parameters for a dual-loop DPLL which achieves the fastest initial acquisition time by trying to minimize the jitter variance in any given time instant.
This dissertation also proposes a low pow...