Analysis and architecture design of power-aware H.264/AVC encoder using power-rate-distortion optimization

Abstract

Portable video communication devices or wireless video sensor networks (WVSN) operate on batteries with limited energy supply. However, a video compression is computational intensive and energy-demanding. Therefore, one of the central challenging issues is to minimize the energy consumption of the video encoding so as to prolong the operational lifetime of portable devices or video sensors. In this paper, an architecture of power-aware H.264/AVC encoder is proposed, which can provide outstanding coding performance and thus suitable for portable devices or WVSN. To reduce the power consumption, two low-power techniques are applied. First is reducing the DRAM access by using a lossless embedded compression (EC). Second is reducing the logic switching power through the bit-truncation scheme applied integer and fractional motion estimation. About 80% of the power consumption is reduced through these two low-power techniques. In a wireless transmission system or a portable device, the power-rate-distortion (P-R-D) optimization is necessary to prolong the operation lifetime under energy constraints. Therefore, the P-R-D model of the video encoder is provided with two steps. First is the modeling process of the relationship between the power consumption and distortion (P-D). To model the power consumption of the video encoder, the power consumption of each functional module is analyzed. Second is generating the unified P-R-D model based on the P-D model. Experimental results show that the proposed P-R-D model represents the relationship among power, rate, and distortion accurately. With the P-R-D model, a designer could optimize the video encoding system by allocation proper power resources to video encoder and wireless transmission or storage system while the distortion is minimized.