(A) high-performance memory interface using high-speed off-chip data transmission techniques = 고속 칩 외부 데이터 전송 기법들을 이용한 고성능 메모리 인터페이스 연구

Cited 0 time in webofscience Cited 0 time in scopus
  • Hit : 331
  • Download : 0
As the clock frequency of the central processing unit (CPU) is greatly increased to process multimedia information, the amount of data to be sent to an external memory has been increased as well. The memory input/output bandwidth also must be increased to process large amount of data. However, the design of a multi-gigabit memory transceiver using a conventional circuit topology can be challenging. Meanwhile, the crosstalk becomes the major noise sources in memory interface since a parallel off-chip bus topology is generally used in a memory interface in order to maximize memory I/O bandwidth. The coupling of energy from one channel to another which is called crosstalk causes the serious impairment of data. Hence, the crosstalk impedes high-speed data transmission above 5-Gb/s in a memory interface. A 3.2-Gb/s/pin transceiver for DDR memory interface is implemented with a low-jitter digital DLL and a MUX embedded pre-emphasis circuit. The DLL achieves the lock operation by a Coarse-Control Part and a Fine-Control Part. The Coarse-Control Part coarsely selects the edge of the output clock based on a digital counter. The Fine-Control Part precisely determines the final edge according to the edge selection information from Coarse-Control Part. The proposed DLL selects the output clock edge which is closest from the edge of the reference clock. The delay range covered by the Fine-Control Part is reduced by a half compared to the conventional edge selection scheme. The DLL repeatedly selects output clock edge which is closest from reference clock edge to reduce the total jitter. The transceiver implements a pre-emphasis circuit with a simple structure and less power consumption maintaining high performance. Moreover, the MUX is controlled by a pulse from pulse generator to remove unnecessary glitches of internal node. The receiver samples the received data with an over-sampling scheme that enables a stable tracking and capture of input data. The decision feedback ...
Kim, Lee-Supresearcher김이섭researcher
한국과학기술원 : 전기및전자공학전공,
Issue Date
309332/325007  / 020045156

학위논문(박사) - 한국과학기술원 : 전기및전자공학전공, 2009.2, [ vii, 118 p. ]


Memory; High-Speed; Interface; Wireline; DLL; 메모리; 고속; 인터페이스; 유선통신; 지연동기루프; Memory; High-Speed; Interface; Wireline; DLL; 메모리; 고속; 인터페이스; 유선통신; 지연동기루프

Appears in Collection
Files in This Item
There are no files associated with this item.


  • mendeley


rss_1.0 rss_2.0 atom_1.0