Single-chip programmable platform for system-on-a-chip design시스템 칩 설계를 위한 싱글 칩 프로그래머블 플랫폼

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Today’s embedded systems design culture produces custom products from scratch. However, as electronic products become more complex and global competition demands shorter time to market, the industry is moving toward a design process that integrates commodity system-on-chip (SoC) platforms. This paper presents a rigorous methodology for platform-based software-centric design a two generation of single-chip programmable platform for the proposed design methodology. The first-generation platform (SPP) includes a 32-bit multithreaded RISC processor (MT-RISC), configurable logic clusters (CLCs), programmable FIFO memories, control circuitry, and on-chip memories. For rapid thread switch, a multithreaded processor equipped with a hardware thread scheduling unit is adopted, and configurable logics are grouped into clusters for IP-based design. By integrating both the multithreaded processor and the configurable logic on a single-chip, high-level language-based designs can be easily accommodated by performing the complex and concurrent functions of a target chip on the multithreaded processor and implementing the external interface functions into the configurable logic clusters. A 64-mm2 prototype chip integrating a four-threaded MT-RISC, three CLCs, and programmable FIFOs, and 8-KB on-chip memories is fabricated in a 0.35-mm CMOS technology with four metal layers, which operates at 100-MHz clock frequency and consumes 370mW at 3.3-V power supply. The second-generation platform (SPPA) includes a 32-bit multithreaded RISC processor (MT-RISC2), hardware RTOS support, SIMD processors, IO processors, DMA controller and on-chip memories. While the SPP provides the basic features of the real-time OS, SPPA accommodates nearly full features of a commercial real-time OS including scheduling, various inter-task communication method. SPPA employs a single-chip multi-processor architecture containing an array of SIMD processors and IO processors. SIMD instructions nearly doubl...
Advisors
Park, In-Cheolresearcher박인철researcher
Description
한국과학기술원 : 전기및전자공학전공,
Publisher
한국과학기술원
Issue Date
2005
Identifier
249501/325007  / 000995174
Language
eng
Description

학위논문(박사) - 한국과학기술원 : 전기및전자공학전공, 2005.8, [ vi, 85 p. ]

Keywords

Multithreaded Processor; Design Methodology; Platform-based Design; Programmable Logic; 프로그래머블 로직; 멀티쓰레디드 프로세서; 설계방법론; 플랫폼

URI
http://hdl.handle.net/10203/35330
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=249501&flag=dissertation
Appears in Collection
EE-Theses_Ph.D.(박사논문)
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