Low power on-chip memories using low swing techniques

Abstract

As mobile systems such as personal digital assistant, notebook computer, and wireless phone become very popular and demand high-speed and complex functionalities, power consumption has become an important design criterion of VLSI chips. On-chip memories such as static random access memory (SRAM), read only memory (ROM), and content-addressable memory (CAM) consume a great deal of power in these systems. In this thesis, we propose several techniques to reduce the power consumption of on-chip memories. The proposed techniques are the SRAM using hierarchical bit lines and local sense amplifiers (HBLSA-SRAM), the ROM using a single charge-sharing capacitor (SCSC-ROM), the CAM using the pulsed NAND-NOR match-line and charge-recycling search-line (PNN-CAM), and the area-efficient charge-recycling predecoder (AE-CRPD). The HBLSA-SRAM is proposed to reduce the write power dissipation of bit lines by reducing the swing voltages of bit lines. The new hierarchical bit line structure with the local sense amplifiers reduces the ``bit line capacitance and the swing voltage of the bit line during write cycles. The HBLSA-SRAM reduces the write power by applying the low swing voltage signal to the high capacitive bit line and by applying the full swing voltage signal to the low capacitive sub bit line. The hierarchical bit line reduces the leakage current and improves the noise margin in bit lines. The HBLSA-SRAM with 8Kx32bits consumes only 66% write power of the conventional SRAM. The SCSC-ROM is proposed to save the power consumption of bit lines by using the new charge-sharing technique. The SCSC-ROM reduces the swing voltage of bit lines to the minimum sensing voltage of sense amplifiers. The SCSC-ROM uses a single capacitor to reduce the swing voltage so that the SCSC-ROM is not only robust against noises but also easy to design. The hierarchical word line decoder reduces the power consumption of the control unit and predecoder of the SCSCROM. The hierarchical bit line re...