Design of sigma-delta modulators with calibrated mixed-mode integrators

Abstract

This thesis presents a sigma-delta modulator architecture, which is suitable for realizing high-order sigma-delta modulation with analog circuits of limited dynamic ranges. The architecture is based on a mixed-mode integrator that is a combination of an analog integrator and a digital integrator. The use of mixed-mode integrator helps make the resulting sigma-delta modulator stable. The architecture, however, relies on precise matching between analog and digital paths. A calibration technique is proposed to mitigate the effects of the mismatch. In order to verify the proposed architecture, a prototype third-order sigma-delta modulator employing mixed-mode integrators has been designed and implemented in 0.18um CMOS process. The modulator is designed to cover the required dynamic ranges for GSM and WCDMA applications. Because the use of mixed-mode integrators allows a 12 dB improvement in the dynamic range over conventional architectures, the modulator can be driven by relatively low sampling frequencies. Measurements show that the prototype chip successfully meets the required specifications. The circuit occupies 0.7mm$^2$ silicon area and dissipates 4mW from 1.8V supply voltages.